I've had a hunt and can't find any component that matches my requirements, so maybe I'm not just searching for the correct name.
Essentially I'd like some sort of FIFO memory. It would have eight data lines for input and a control pin to clock in data. It would then have eight pins for output and a control pin to clock out data. Ideally the output port would also be tri-stated to make it easier to attach to a CPU's data bus, though this is not essential as the same effect could be achieved with an additional tri-state buffer or latch IC.
Finally, a pin that changes state to indicate whether the FIFO contains either zero or more than zero items would be useful.
The FIFO doesn't need to have much memory (though more than one data word would be useful, otherwise I could just use a latch!) It would be useful to interface other components (such as microcontrollers) to a microprocessor system where the microcontroller would not be fast enough to respond to conventional I/O read or write cycles; the microcontroller would clock data into the FIFO as and when it needs to, and the microprocessor checks the FIFO state and reads in data as required.
Essentially I'd like some sort of FIFO memory. It would have eight data lines for input and a control pin to clock in data. It would then have eight pins for output and a control pin to clock out data. Ideally the output port would also be tri-stated to make it easier to attach to a CPU's data bus, though this is not essential as the same effect could be achieved with an additional tri-state buffer or latch IC.
Finally, a pin that changes state to indicate whether the FIFO contains either zero or more than zero items would be useful.
The FIFO doesn't need to have much memory (though more than one data word would be useful, otherwise I could just use a latch!) It would be useful to interface other components (such as microcontrollers) to a microprocessor system where the microcontroller would not be fast enough to respond to conventional I/O read or write cycles; the microcontroller would clock data into the FIFO as and when it needs to, and the microprocessor checks the FIFO state and reads in data as required.