It seems some information regarding the TI-81 & TI-86 (& thus probably TI-85) timing is incorrect, at least based on the calculators I have.

TL;DR: The rev. B TI-81 & the TI-86 have the same clock speed. Their CPU has an extra wait state for every M1 cycle. The TI-86 spends about 1/16 of its time doing LCD DMA, interrupting the CPU once per row.

I have a TI-81 with date code I-0393B & ROM 1.8K, which according to DATAMATH should have a T6A43 like the TI-85 & TI-86. I also have a TI-86 with date code I-1197E & ROM 1.4 & another TI-86 with date code S-0402K & ROM 1.6. Anything I say about the TI-81 is specific to revision B, since earlier & later ones had different ASICs. The two TI-86es seem to behave identically, so I mostly tested on the earlier one (due to other having many missing rows on its display).

They all have memory-mapped graphics, & I decided to determine how the LCD DMA interacts with the CPU. On the TI-86, reading from any page in the $80-$FF range seems to usually return the last byte of the opcode (indicating it is unmapped), except for occasionally reading something else. I determined that the something else is drawn from the last column of the LCD, indicating that it happens when LCD DMA interrupts the CPU during the memory read, & that the DMA transfers a row at a time. (This also indicates it can pause the CPU in the middle of an instruction.) But reading from that range on (my) TI-81 always returns 00, so perhaps the ASIC is slightly different, or perhaps some other chip that differs from its 86 counterpart is weakly pulling the data lines low.

The delay between such interruptions seems to vary over a small range. I initially assumed the instruction timings matched a standard Z80, but to make sense of the numbers, it seems that there must be an extra cycle for every M1 cycle, but not non-M1 fetches or other memory accesses, nor for in/out. This is also borne out in how long ASM loops take to execute, even with interrupts & the LCD disabled (& thus no other sources of delay), & it happens on both the 81 & the 86. (Incidentally, it seems no existing 81/85/86 emulator accounts for this.)

With that taken into consideration, the CPU seems to execute 948-958 cycles between DMA of consecutive LCD rows, including between row 63 & row 0 (that is, there is no extra delay for vertical retrace). The variation seems to be random, as it can change for the same code with the same image on screen, but it could depend on something like the battery state. It is possible that other delay values can occur but happened not to in my testing. Values near the previous one seem more likely than far away values, suggesting it is caused by one or more components drifting over time. I have no good way to measure the row timing on the TI-81, which is unfortunate because it probably differs due to having fewer columns.

A loop that takes 15 seconds on the 86 with the LCD off (& thus DMA disabled) takes 16 seconds with it on, which makes me think that the rows happen every 1024 cycles, with 64 cycles taken up by DMA & not quite the full remaining 960 available to the CPU due to overhead of some sort. 64 cycles for DMA makes sense: there are 16 bytes to copy, but écran.pdf in this post suggests that the interface to the LCD board is only 4 bits wide (which agrees with the LCD board images on DATAMATH), & also that the LCD board is clocked at 2.6 MHz, which is close to half the CPU clock, for a total of 4 cycles to transfer each byte. (Another possibility if 2.6 MHz is accurate is that the difference between that & half the CPU clock accounts for DMA taking slightly more than 64 cycles.)

Another big surprise is that the TI-81 seems to have the same clock speed as the TI-86 (tested with interrupts & the LCD disabled), but the resistors attached to the oscillator inputs are all 2.7 kΩ in the images on DATAMATH, & evidently the capacitors are also the same. I measured the clock speed on the 81 to be about 5.6 Mhz & on the 86 to be about 5.5 MHz (but the 81's batteries may be newer).
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