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This is intended to be interfaced with and arduino mega.

Left is the z80, right is AS6C1008 128kb ram chip. Middle is a paging circuit using two NAND gates. Its a bit weird but does what i want. Ram is split into 32kb pages, the z80 can of course address two banks, and the ram chip has 4 pages. When the z80 addresses bank 0, page 11 is always selected. When the the z80 address bank 1, the page 00, 01, 10, or even 11 gets used, depending on the status the PAGE_0 and PAGE_1 lines.

M1, RFSH, WAIT, and HALT are left NC, while NMI and INT are tied to 5v. The clock signal is, of course, connected to the CLK pin. The "3pin_cap" is a full can oscillator, such as https://www.jameco.com/z/OSC4-4-MHz-Full-Can-Crystal-Oscillator_27967.html (and is incorrectly marked "as 3pin_cap" not "3pin_can"). To pause the z80 while it performs operations, the arduino will stop the clock by setting the pin connected CLK_ENABLED to low. The other unmentioned z80 pins (as well as the data and address buses) are connected to the arduino for control.

Just posting this becouse some people here seem to doubt my ability to engineer circuits and i wanted to make sure I wasn't making a major mistake before ordering parts Laughing
Your oscillator is specced to draw up to 50 mA, which is a lot to be pulling out of a microcontroller GPIO. You'd be much better off putting a more proper switch on it (like a P-channel FET controlled by your external microcontroller) or (easier) getting an oscillator that includes an OE (output enable) input.

Schematic-wise (probably not important if you're building everything by hand), your buses aren't actually connected to the pins they're on top of. Kicad requires that every connection to a bus use a wire to bus entry and be labelled with the signal name. For instance:
Most 4-pin oscillators I know have an output enable pin. Might also be more consistent timing-wise, but I don't work with these devices often.

Don't forget your decoupling capacitors! If you're powering this from the Arduino, there's probably capacitors already in place. Maybe I'm just paranoid.
What the proper term for a 4-pin oscillator? I cant seem to find any for sale. Also, apparently full can oscillators such as the one I linked ( https://www.jameco.com/z/OSC4-4-MHz-Full-Can-Crystal-Oscillator_27967.html ), are "ttl". I know the difference between CMOS and TTL, but am not sure what to do about the oscillator.
c4ooo wrote:
What the proper term for a 4-pin oscillator?
It's just an oscillator.

Quote:
Also, apparently full can oscillators such as the one I linked ( https://www.jameco.com/z/OSC4-4-MHz-Full-Can-Crystal-Oscillator_27967.html ), are "ttl". I know the difference between CMOS and TTL, but am not sure what to do about the oscillator.
Jameco's terminology is not very helpful, since "full can" is only referring to the package. In this instance TTL refers to 5V logic.

I found 6 parts that Digikey stock and meet your general needs (4 MHz xtal with OE input and in a through-hole package).
Thanks, finding parts on digikey is so easy compared to jameco Very Happy
Anyways, this is more of a list for myself for future reference, but the parts i plan to buy:

128kb ram - https://www.digikey.com/product-detail/en/alliance-memory-inc/AS6C1008-55PCN/1450-1017-ND/4234576
oscilator - https://www.digikey.com/product-detail/en/abracon-llc/ACO-10.000MHZ-EK/535-9203-5-ND/675398
z80 - https://www.digikey.com/product-detail/en/zilog/Z84C0010PEG/269-3898-ND/929206
nand - https://www.digikey.com/product-detail/en/texas-instruments/CD4023BE/296-2041-5-ND/67265

Here are new schematics:
So I was recently reviewing some of these, and a concern came up:

The output from the NAND gate is connected to both the second NAND gate and, via IOREQ, to an Arduino PIN set to INPUT. Is this OK?
Furthermore I assume that connecting one of the z80's outputting control pins (M1) to multiple as an input to multiple gates is fine, right?
ERC knows what's up (these are kicad's default ERC rules):


Connecting output to input is OK, and output to output is an error. Input to input is also okay. The pictured net could be considered as the following pairs:

(out, in)
(out, in)
(in, in)

each of which is legal.
  
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