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I'm working on a CPU design, and I'd like some advice on what instructions I should put in it. I have a few ideas on what I definitely want, but not enough to make a full CPU.

A few I definitely want: (feel free to convince me otherwise if you have a good reason to do so)
PGT (an idea I had Razz basically it allows for up to 4 times more RAM addressing by doing a RAM paging method reminiscent of the 84's, where activating this command switches pages and leaves only a small portion of the RAM, or even just the registers, present.)
Ways to manipulate memory and registers

But I only have 2 bits (it's in base 4) so it gets a little complicated. For instance, let's say I want to load something to a register, and registers are only 1 bit (from 0 to 3). That would mean I would have four of my registers taken up with setting it to that specified value, unless I cheat like I did with my old version in an emulator Razz

Any suggestions?
Well, for the PGT instruction, it sounds like it would be more device specific (for devices that actually can work with that much memory, and in that way). It's an interesting idea, though Smile For a comparison, the 16-bit mode on the x86 uses segmentation to achieve this; it works so that if DS holds an address like 0x5000, and the program pointer one holds an address 0x6000, it means you're referring to address 0x56000, not 0x6000.
This is going to be very device specific Wink but that does sound similar to what I'm looking for, advantage to it being that you can access the memory in a more linear way, whereas my idea separates the segments a lot more.

Odd thought: How does the intel 4004 (a 4 bit CPU) get more than 16 instructions??? [/envy]
The 4004 has 8-bit opcodes. Instructions don't need to be a fixed size; literal data can be appended, for example, or a prefix could change the behaviour of the instruction (the Z80 uses this, for example, to switch between acting on HL, IX or IY in certain instructions).
Sounds like homework. I'm not sure we should help.
It's not homework Razz I'm only a senior in High School with no current tech classes. This is for a science fair project.

Also, I've been thinking of keeping a feature I had in my old version: a set of addressing bits. Basically, it extends it to 4 bit opcodes, but only uses 16 commands and sends the last 2 bits as effective arguments, determining various things such as what register, memory location and whatnot.
One thing I always try to keep in mind when designing very low-level logic things is that everything can be created with NAND gates or operators. This reminds me of another custom microprocessor project around here; I think it was by Adept.
Yes, I do remember someone asking about instructions to make an instruction set "fun" a couple months back. Here it is" http://www.cemetech.net/forum/viewtopic.php?t=6703&highlight=instruction
Also my research paper, which includes a rather odd design. 8-bit core with fixed-length 24 bit instructions.
The important thing to keep in mind (as others have mentioned here) is that your instructions don't need to be the same width as the data the system works with. In my design, I envisioned a 24-bit bus for program memory access (mainly to avoid variable-length instruction encoding) with 8 bits on the main data bus.

I think things like memory paging are better handled with obviously external peripherals rather than in the core itself. You can do any number of tricks with memory-mapped I/O.
well, mine really can't all be built by NAND gates since it's not binary. Using only NAND gates is kind of cheating anyways Razz but the CPU is mainly to demonstrate the base 4 hardware that I designed in action.

So here's what I'm thinking as of now:

Note - x = register's value, val = direct number input, r = register address (for altering said address)

There are 4 registers which each hold 2 bits (0-15), but are referenced by 1 bit (0-3) Therefore you can reference 2 registers in one command but only one val

AND x,y- Does x AND y and stores it into A
OR - See AND
NOT x - Returns the bitwise NOT of x, into A.
IF val - tests if A is equal to B, and if so, trips a flag that skips any code until a TIF with the same x is found. This allows up to 16 nested IF statements.
TIF val - ends an IF, if nested in one of the given x, otherwise behaves as a NOP. Good to have at the end of a program, repeated for 0-15, to prevent crashes and mem leaks.
STO x - stores x at the address CD (Using CD makes programming simpler than AB)
RCL r - recalls what is stored at CD to register r
INS val - puts the specified val into A
CP x,y - copies register x's value to register y's value

This still leaves some holes, for things like returning to earlier parts of the program, and subroutine-ish functions. I'm thinking I should also have an "execute from RAM" mode as well, but that could get messy fast.
So, I've actually finished the simulator (about 2 weeks ago actually, but I've been busy winning the science fair I entered it in) and here's the set I decided on:

HLT - stops the sim
LD - Loads fed value to A
LDR - Loads RAM value read to A
STR - Stores A to RAM
RTR - Stores 1st reg to second
JMP - standard jump, but relative so I'm not restricted to 256 lines, with some extra features
RET - Part of the extra features of JMP

And I left the other 3 slots open for other options. right now I'm thinking BUP and BDN, non-wrapping shifters that take 22 to 33 and 11 respectively, but BUP would leave 33 at 33 and 00 at 00.

With enough work I think I could make conway's GOL in this, but I'm planning on doing a Sierpinski generator (only 1 in above 3 to go on) first. 256 2-qit RAM slots double as a display, but sections could easily be dedicated to IO for a binary ram chip and LCDs, etc. Basically the RAM is meant to act as the interface for everything else.
Hmm, so you only have two registers present? Also, I notice you have no stack operations at all (unless RET/JMP have address push/pop connotations?) Honestly, a processor with no stack capabilities sounds extra painful to program for, especially if you only have one or two GPRs!
four registers, not two, capable of holding a value from 0 to 15 each

And no, there's no stack stuff, but it's not hard to remember where you left your variables when you only have 16x16 memory slots.

And of course it's painful! It's only a 2-bit cpu!
If it's base-four, I don't think “bit” is the right word. It's not a binary digit anymore. Wink
Travis wrote:
If it's base-four, I don't think “bit” is the right word. It's not a binary digit anymore. ;)

quibit, no? That'd add an exponential speed increase.
well, I've been using 'digit' a lot, since bit just means 'binary digit' but as far as I can tell the best choice is either 'nybble' (2 bits) or 'quit/qit' (the 'b' comes from binary.)

All that is just semantics. Razz I just care about the tech.
Well, it's important to be clear. Smile I was initially confused when I read “bit” until I realized that you weren't merely talking about using two-bit states but actually using true four-state hardware for each digit.
True, true.

I still don't see a point in having any type of stack operations, myself, since there is so little space to begin with. Adding a RAM module would require special access methods anyhow, so I think I'll leave it up to the programmer to develop a memory management routine that suits their setup.
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