Quick question. I was looking at the CMOS circuit diagram for the And and Nand gates, and I was confused as to why And was built from two P-types and two N-types when one N-type is essentially an And gate in itself and a P-type is essentially a Nand gate.

Edit: I realized after I posted this that a P-type transistor does not function like a Nand gate...thanks for the answer, though. It's a bit over my head because I'm not an Elec Eng major, but I think I got it.

The signal going into the source of a FET will be forced to source enough current to drive all the parts downstream of it.
On a typical CMOS circuit, the transistors have basically no ability to drive large loads (which is why the external connections are nearly always driven by large buffers), so instead of driving the current to run every part downstream of that gate through each gate, complementary FETs are used to directly connect each signal to either the positive supply or ground, so any appreciable current will be sourced from the supply rails rather than from an upstream gate.

I also suspect it may be related to the non-ideal properties of a real FET, but that seems less concerning than pulling large currents through small transistors.