Just to put in my 20 millibucks, I think what makes an ISA fun is orthogonality. That is, any instruction can operate on any register (including "special" registers like the program counter and status register). It's often easier to make a smaller instruction set when they are orthogonal than by having a bunch of special instructions and special registers (I guess this is basically a RISC vs CISC comparison).
One thing that I think is cool is, instead of including an instruction for each type of operation (add, subtract, multiply, divide, etc), set aside special registers or memory locations that give the desired results when read back. For example, using special registers, r0 and r1 are the operands, r2 is the operation register, and r3 is the result register; after loading the values into r0 and r1 and the operation code into r2, reading from r3 gives the result. Since the result might not be available before the next instruction execution time, another instruction could run (one that doesn't read from r3) in the meantime before r3 is read back. This can avoid instruction pipeline stalls (if you choose to get that sophisticated with your ISA).
Orthogonality, of course, results in some nonsensical instruction opcodes, but sometimes those can be put to good use by some clever programmer!
On the other hand, as I think Qwerty.55 suggested, you could include only 8 instructions: < > [ ] + - . ,
Last, why not implement a One Instruction Set Computer (OISC) machine? As its name implies, it has only one instruction, so the opcode itself can be omitted; only the operands need to be specified. A few years ago I personally implemented the "Subtract and branch if less than or equal to zero" type in Z80 assembly. The interpreter itself was fairly small (only 60 bytes or so). See http://en.wikipedia.org/wiki/One_instruction_set_computer#Subtract_and_branch_if_less_than_or_equal_to_zero