Taking everything that I learned this last year and everything that I'm learning right this moment, I am proud to announce my second years beginning for a CPU design. The major change this year is the scale, which is possible to be larger because I am learning Verilog and am using an FPGA. A single board will be all that is necessary this year. It will be as if making it from discrete gates, except that they are packaged even smaller. The architecture is being re-designed to be more practical, including the majority of the x86 instruction set. The board the FPGA is sitting on will contain a UART to USB to enable the use of USB devices, and an old RS232 will interface with the mouse and keyboard. (I am following an ancient schematic for a z80 computer to help me design the keyboard interface, that's why RS232.) The display driver has already been designed in Logisim, and functions perfectly well, with a refresh rate of about 6Hz at 4.1KHz simulation speed. The design is implementing DDR RAM chips and PCI slots, along with the old EIDE and PATA technologies for mass storage of files and programs. The majority of the essential commands have been simulated in Logisim at the moment, and is almost ready for a test, of which I will post up a link for Cemetechians to explore. For anybody who this means anything too, the CPU has a 16-bit word size. (Which really means nothing anyway, because there are numerous things you can do to get around that limitation.) I hope to be posting up lots of information, and eventually the Verilog source code, so anyone can do it like I did. And FPGAs really rock because you can reprogram them if you mess up the first time, they can be clocked at many MHz, and they don't require a bagillion hours of soldering to build. (Heck, development boards require NO soldering at all! (Arduino-like, huh?))

So, wish me luck everyone! (I'm on an adventure in Odyssey!Very Happy)

There won't be a testable version for a while yet because I am making it modular. This means that if you stack them, the word size is increased, if you stick 'em sideways to one another the speed is increased. I have modularized the stupid easy things to modularize. (Adders, counters, etc.) Working currently on the hard stuff though!
FPGAs sound like a wise path. I like to design and build using discrete components or logic chips for fun and for hobby, but FPGA type tech is were you can grow easily. I recreated my quadrapod schematic on a Xilinx CPLD and added some features, and that was on the smallest chip in the product series. I accidentally stumbled upon your other thread discussing the CPU you built. I'm glad my logic work inspired you!

I may be new to this forum, but I see that some of my old work has been here for a while! I'm glad to have put that knowledge out there for people to see!
Richfiles, yup, many of us have learned a lot from you over the years, so thanks very much for all your teachings, even though you didn't directly know we were learning from you. Smile I agree that using FPGAs would be a good approach to take; I've had a lot of fun using FPGAs for various applications. Can I assume that you are using one of the FPGA dev boards that the FPGA companies make available for academic applications?
I have a single Xilinx dev board, but I rarely use it. I tend to make my own circuit boards for stuff. Then i can test changes in the final application, from the start. I have this tendency to plan a circuit to completion before building. Also hopelessly attached to paper when designing! Haha! My design techniques are so primitive! LBP2 and Xilinx's software are where I do most digital design. Unfortunately, my PC died some time ago, and I havn't replaced it (on an ancient Mac right now), and I haven't touched eagle or Xilinx's software for ages. I really need to replace that thing!
Richfiles, I wish that I could get more into custom fabbing of boards for my projects. They're so often one-off prototypes that I usually just end up slicing up perfboard and doing judicious trace bridging and cutting.
The very circuit that started adept's first CPU thread was routed on paper, and laid out on copper clad board using dry transfer decals and etched. It's a lot of work, and for some reason, I have a knack for routing schematics into circuit boards on paper, but the result is undeniably nice. If I ever get my PC going, I'll return to using Xilinx CPLDs and Eagle for doing PC boards.

Here are the links to some VERY OLD scanned images of the two boards that make up my Quadrapod control circuit. It was all hand done. Now, I'd fork out for a cheap board service. I don't have that kind of free time anymore.

Routing PCB
Control PCB

Those are pretty old designs. I have actually converted all that to a single chip using a Xilinx 9536 CPLD. The 6 stage "loop" in the schematic is a "BEAM" style Nervous Network... Aka, a simple pattern generator. The circuit is a 6 step relaxation oscillator that has some analog attributes that allow you to change the duration of steps and leg motions. In theory, you can even directly influence the walking gait with simple components like potentiometers.

Currently, I am trying to build a tube based calculator out of 1960's era parts, as well as a LBP2 virtual calculator.

If I ever find the diagrams (though I can easily recreate them from memory), my second latest random digital logic project was to create a low grade "neuron" circuit to form a very rudimentary adaptive connection memory. It uses Xilinx 95xx series CPLDs with a few analog support components. The resolution can scale depending on the desired complexity, but I stuck with 5 bits of resolution. 32 steps is probably sufficient for my low grade robotics experimentation. The basic premise is to pair two accumulators and a digital comparator. One accumulator is the Synapse Input accumulator, and the second is the Neuron Weight accumulator.

The Synapse input accepts pulses or analog signals from multiple inputs, filtered through a diode/resistor/capacitor/schmitt trigger (similar to the "BEAM" style relaxation oscillator). There is an input that accepts a pulse input that determines input sensitivity. The input pulse, eventually reaches the synapse accumulator. Each excitatory pulse increases the accumulator by 1 and each inhibitory input decreases it by one. When the synapse accumulator equals the weight accumulator, the synapse accumulator is reset to zero, and an output pulse is fired. In addition, the weight accumulator decreases by one digit.

The circuit also relies on a Weight Decay Rate input, and a Synapse Decay Rate input. These are a single bit input who's pulse rate sets the rate that the neuron's activities fade. If the neuron has little activity, the weight will slowly drift back up, and if no inputs are received, the charge on the synapse can also be set to fade as well. Every time the neuron fires, the weight decreases and it becomes easier to fire with fewer pulses. If it does not fire, the weight increases and it takes more pulses to fire.

I wanted to merge these types of virtual neurons with BEAM style circuits. Most BEAM circuits are simple pattern generating loops. I and others have experimented with branches that break off from loops, branches that fork multiple times, and even matrixes of nodes. A few others have done layered loops.

It's been a while since I've worked on that stuff. Mainly due to time money and the failure of my PC. I want to get back into it, but Right now... Too many responsibilities to worry about recovering old projects. It's such a pain!
I must say that I am impressed with your projects Richard. I think I will return your story with another.

I got my first calculator in 7th grade because I was in the 2 years advanced in math program, and was already in Algebra I. It didn't take long for me to find TICalc.org and start playing around with my calculator. Under the hardware tab, I found your website, the Richfiles, and read every page within.

Now, my very first electronics project was building your SpinTerFace. I built just about every circuit on that site, inside my teachers TI-85 that she gave me.I got into robots after reading about your robots, and set out to make one. My first robot looked like this:

Uploaded with ImageShack.us

That robot was the first complex design I made. (Its processor is an ATMega8) So thats when I found your Quadrapod schematic, and decided to go about making my own CPU. You have no idea how similar your design was to a CPU, they are like twins. You had 4 different commands, mine had 16, for example.

Just thought you might like to know.
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